Company Breakdowns: Quilter with Benchmark's Eric Vishria

Published

June 13, 2024

Written by

Sergiy Nesterenko

Founder and CEO

Read the Full Series

This article is one part of a walkthrough detailing how we recreated an NXP i.MX 8M Mini–based computer using Quilter’s physics-driven layout automation.

Overview: Project Speedrun

Part 1: Preparing the Design

Part 2: Compiling the Design

Part 3: Cleaning Up the Design

Part 4: Testing & Validation

Eric Vishria, General Partner at Benchmark, and Sergiy Nesterenko, Founder and CEO of Quilter, join Nathan Labenz to discuss Quilter's groundbreaking use of reinforcement learning to automate integrated circuit board designs.

They delve into the importance of thinking beyond 'co-pilots' to fully automated AI solutions, and explore the balance of research and engineering in the AI space.

TIMESTAMPS:
(00:30) Introduction
(01:07) Eric's Investment Thesis
(03:00) The "AI and Done" Approach
(06:50) Diverging from Large Language Models
(09:15) The "Idea Maze" Framework
(11:54) Disruptive Innovation
(12:47) Sponsor: Brave | Babbel
(15:09) Exploring the Data Landscape
(16:18) Data Limitations and Reinforcement Learning
(18:00) Overcoming the Sparse Reward Problem
(19:10) Human Heuristics and Intermediate Rewards
(21:06) Extrapolation vs. Interpolation
(24:37) Trusting the Reward Signal in Circuit Board Design
(25:46) Physics as an Unambiguous Oracle
(27:05) User-Defined Search Depthbility to adjust the search depth and iteration of the system, enabling flexibility based on design complexity and optimization goals.
(29:39) Compute Allocation
(31:47) Different Physics Simulation Techniques
(33:31) The Diffusion Model Approach
(36:00) Advantages of Reinforcement Learning
(38:00) Timeline and Bottlenecks
(39:37) Unsolvable Problems and Gradual Progress
(41:58) The Future of Circuit Board Design
(43:29) Benchmark Portfolio
(45:00) Challenges and Opportunities in Each Category
(51:00) The Gap Between Research and Engineering
(53:00) Call for Startups
(54:06) Wrap

Try Quilter for Yourself

Project Speedrun demonstrated what autonomous layout looks like in practice and the time compression Quilter enables. Now, see it on your own hardware.

Get Started

Validating the Design

With cleanup complete, the final question is whether the hardware works. Power-on is where most electrical mistakes reveal themselves, and it’s the moment engineers are both nervous and excited about.

Continue to Part 4

Cleaning Up the Design

Autonomous layout produces a complete, DRC'd design; cleanup is a brief precision pass to finalize it for fabrication.

Continue to Part 3

Compiling the Design

Once the design is prepared, the next step is handing it off to Quilter. In traditional workflows, this is where an engineer meets with a layout specialist to clarify intent. Quilter replaces that meeting with circuit comprehension: you upload the project, review how constraints are interpreted, and submit the job.

Continue to Part 2