TL;DR; Traditional autorouters measured success by completion: how many nets they could connect without violating design rules. But a 100% connected board isn't necessarily a working board. It can pass a Design Rule Check (DRC) and still have return-path discontinuities, poor impedance control, excessive coupling, or assembly issues.

The core lesson of sixty years of PCB layout automation is that connecting pins is not the same as producing a board an engineer can trust.

The real task of a PCB layout automation tool is to reduce the work required to get a manufacturable board. To achieve that the next generation of tools has to solve a harder problem. It has to solve placement and routing as one coupled problem, evaluate placement and routing candidates against the electrical behavior of the finished board, and explore enough alternatives to find workable layouts. 

Given the long history of attempts to automate PCB layout, we are well aware of the skepticism that exists in the industry, and that “is it another autorouter?” is one of the first thoughts that comes to engineers’ minds when they first hear about Quilter.

This article examines why PCB layout automation can finally move beyond the limitations of traditional autorouters and how Quilter is trying to do exactly that.

Autorouter vs. AI Layout Automation at a Glance

What Is a PCB Autorouter?

A PCB autorouter is a software tool that takes a board with components already placed and connects the nets between them in copper, on a grid, against a set of constraints. The first version of a maze-routing algorithm was published in 1961. Commercial autorouters have shipped inside Cadence Allegro, Altium, Siemens Xpedition, and from other vendors. Engineers have, just as consistently, learned not to trust them.

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Ask a PCB designer with twenty years of experience about autorouters and you'll get a version of the same story. They set it up, let it run, and got back something that looked like spaghetti thrown at a wall. Cleanup took longer than starting over, so they turned it off. Some of them wear T-shirts that say "never trust the autorouter." (EEVblog Forum 2014)

PCB layout can be a very time-consuming and laborious process, it often creates a big bottleneck in the hardware development cycle. It is only natural that a lot of capable people have worked on trying to automate it for decades. And we think it still is a problem worth solving.

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When Did PCB Autorouters First Appear?

The idea of automated routing is older than many of the people designing boards today. In 1961, a Bell Labs researcher named C. Y. Lee published a maze-routing algorithm that could find a path between two points on a grid (Lee 1961). It launched a field. Commercial autorouters followed through the 1970s and 1980s. By 1989, John Cooper and David Chyan had founded Cooper & Chyan Technology and shipped Specctra, the shape-based router that became the reference point for the industry. Cadence acquired the company in 1997 for roughly $400 million, the most expensive EDA acquisition in history at the time (Federal Trade Commission 1997; Goering 2005). An evolved version of Specctra still ships today in some Cadence products.

Faith in the idea ran deep, even among people who knew its flaws. In 2018, our own Ben Jordan, a longtime Altium engineer at the time and EDA industry veteran, hosted a widely shared talk on trusting the autorouter. He opened by conceding that most professional designers he had spoken with would not use one, then made the case that it was a tool worth learning to use well rather than writing off (Hackaday 2018).

Why Has PCB Layout Automation Always Been This Hard?

Layout isn't one problem. It's two problems tangled together.

Placement decides where each component sits. Routing connects them with copper. Both are NP-hard (Yan et al. 2022). The number of ways to arrange and wire a board grows so fast that the solution space is effectively unbounded.

The two halves can't be separated either. You can't judge a placement until you try to route it. The classic autorouter never solved that coupling. It assumed the placement was done, took it as input, and started laying copper. When the routing got stuck, the tool blamed the engineer's floor plan and quit.

Faster chips never closed the gap. Compute followed Moore's Law, doubling every couple of years. But board complexity grew combinatorially as density and constraints climbed. Apple's original iPhone, in 2007, used a pair of stacked boards to fit its electronics into the chassis. Ten years later, the iPhone X returned to the same stacked layout, but the substrates inside were now substrate-like PCBs (SLPs) with conductor widths down to 10 to 15 microns and microvias in roughly the same diameter range (TechInsights 2017). 

The trajectory was the same everywhere: aerospace, defense, automotive, medical, industrial electronics. Each generation of devices brought more layers, denser packing, and finer features. Every layer and every constraint multiplies the interactions a router has to weigh, so the problem outran the hardware even as the hardware sped up.

The hardest part isn't even finding a path. It's density: packing traces side by side across a crowded board so everything fits, while every trace also has to behave the way the circuit requires. 

Chip routing looks similar on the surface, but it runs on a much more regular grid. Every layer has a preferred direction, traces turn only at right angles, vias come in standard sizes, and components are parameterized cells from a library. PCB routing has none of that regularity. Traces can run at any angle. Components arrive in thousands of package types with different pin patterns, keep-outs, and clearances. Via types and design rules change with the fab and the stackup. Vias are also a bigger problem on a board than in a chip. On a PCB, a via almost always has to be 3 to 4 times wider than the traces it connects. In silicon, the via is a solid metal structure about the same width as the trace, which makes it far easier to place and route automatically. Every PCB via takes up much more room than the wire it serves, and on a dense board that space adds up fast. 

There's also a human element, and it's a bigger challenge than people outside the field tend to realize. 

PCB designers care about how a board looks, often referring to the layout as “artwork.” Traces are expected to run at 45-degree increments (octilinear routing), to maintain visual rhythm, to avoid obvious detours, to look like an experienced engineer drew them. None of this is a physical requirement. A board with traces at 37.4-degree angles can work exactly as well electrically. The 45-degree habit is largely a legacy of ECAD systems from the 1980s that couldn't handle routing at arbitrary angles. The constraint is long gone, but the convention remains. 

That isn't to say trace angle never matters. On high-speed boards, for example, fiber weave skew depends on how a trace runs relative to the glass weave in the laminate. One common way to reduce it is to route long traces at a 10 degree angle to the board axes (Simonovich 2011). Another example are acid traps. During the manufacturing process, when two traces meet at 90 degrees angle, the sharp inside corner can trap etchant. If it lingers there, it can keep eating into the copper, narrowing the trace or, on a very thin trace, opening it entirely. The acid trap is one reason designers were taught to avoid acute angles. Modern fabrication has made acute angles less dangerous than they once were, but it is still something worth checking with your fabricator.

But the primary reason designers prefer certain board aesthetics is convention and habit rather than physical requirements, and a tool that ignores it produces output engineers reject on sight, before they check whether it's electrically sound. Worse, the aesthetic isn't universal. What "looks right" varies by company, by team, sometimes by individual reviewer. 

What Did Traditional Autorouters Actually Do?

The classic autorouter was a set of carefully tuned algorithms wrapped in an expert system. 

Maze routers found one net at a time and got blocked when later nets needed the same channel. Shape-based routers like Specctra represented obstacles geometrically and could push existing traces aside to make room. Rip-up-and-retry strategies allowed routers to undo a previous decision and try again. Negotiation-based routers, introduced by McMurchie and Ebeling (1995) for FPGAs, let nets bid against each other for congested resources and iteratively resolve who got what.

Each piece was an attempt to encode what a good designer knows. The way they failed in production was always the same, and it came down to two things.

First, the autorouter turned engineering judgment into a fixed ranking of rules. Keep these traces apart. Minimize vias. Prefer this layer for high-speed signals. Route power first. Each rule was sound on its own. The catch is that a ranking is a guess made in advance. It fixes one ordering of tradeoffs before a single trace is laid, and the tool has no way to revisit it as the board fills in, because it never computes what a given decision does to the circuit. An experienced designer doesn't rank rules in the abstract. They weigh a specific trace against the board in front of them, knowing what can go wrong electrically. The autorouter applied the ranking and accepted whatever came out. 

Second, as we mentioned earlier, the autorouter optimized the wrong objective. The standard internal metric was completion rate: what percentage of nets did the tool connect without violating constraints? Designers know this is the wrong target, a routed board is not the same as a shippable board. Autorouters had no awareness of the physics of the board or the design intent, and had no way of judging how a finished board would behave.

What Should a PCB Layout Automation Tool Be Measured On?

Completion rate, via count, and runtime matter. But they do not prove that a layout candidate produced is any good. A better way to evaluate a layout automation tool is to ask whether the candidates it produces pass DRC, satisfy the relevant physics checks, preserve critical return paths, meet controlled-impedance requirements, avoid unnecessary coupling, and do not require an engineer to spend more time on cleanup than on doing the layout manually.

The real benchmark is whether the tool produces a candidate an engineer can review, trust, and iterate on.

The First Missing Piece: A Way to Reason From Physics

Reasoning from physics means making layout decisions evaluated against what the circuit will actually do, not against a fixed list of rules. The autorouter never had a way to do that. To know whether a routing decision will hold impedance, preserve return paths, or avoid crosstalk, you have to compute the physics of the resulting board. And to do that across many thousands of decisions a board might require, you need a system that can navigate the search space efficiently: propose decisions, evaluate outcomes, learn what works.

The obvious approach of training an AI model on existing board designs cannot work for several reasons. First, a large, public, well-labeled corpus of modern PCB designs just doesn’t exist, most designs of working products are locked inside corporations as proprietary IP. Second, not all PCB designs are created equal, imitation inherits human mistakes and caps the results at a human level. 

That is where reinforcement learning (RL) becomes useful. Define what a good board looks like, generate many candidates, score each against the physics, and let the system learn which decisions get there. This isn't brute force, it's intelligent search. The model uses what it learned from past generated attempts, synthetic training problems, and the problem classes the system has encountered to skip dead ends and spend effort where a solution is likely, the way an experienced designer would.

As a working technology, reinforcement learning is relatively recent. The results that made it credible are less than a decade old: AlphaGo in 2016 and AlphaGo Zero in 2017.

The game of Go is a good comparison to PCB design. Its search space is so large that the tree-search methods that beat human chess champions in the 1990s failed at Go for almost two decades, until DeepMind paired tree search with a neural network that learned which moves were worth considering. The first AlphaGo learned that from human games. AlphaGo Zero threw the human games out, learned by playing itself from nothing but the rules, and beat the human-trained version 100 to 0. DeepMind also trained a version on human data to compare; it learned faster at first but plateaued at lower results (Silver et al. 2017).

That distinction matters for layout. A model trained to imitate finished boards is bounded by the boards it learned from. Give it a design unlike anything in that set, and it falls back on the nearest example it has seen, which may or may not be right. Quilter does not learn by copying customer layouts or imitating finished human designs. Instead, the system learns from generated attempts, synthetic training problems, and classes of layout challenges. Where submitted designs are used to improve the system, they are used according to Quilter’s data-use terms to generate generalized training problems, not to reproduce design patterns (designs from commercial customers are not used in our training pipeline at all, and designs submitted through the free version of Quilter are used to generate synthetic training data).

The Second Missing Piece: A Way to Check the Physics During Layout Generation

Reinforcement learning, on its own, is not enough.

A trained model is good at proposing decisions that look promising. It is not the right tool for calculating whether a specific differential pair, on a specific stackup, with a specific via transition, will hit its impedance target inside the tolerance the design requires. That question needs a solver, not a guess.

Quilter isn’t an AI company that found a problem to point AI at. We started with the problem and picked the right tools for each part of it. Reinforcement learning navigates the combinatorial search, but the candidates it proposes are checked against deterministic constraints, rules, and solver-backed calculations. In that setup, AI is useful because it can search for candidates that pass checks an engineer can understand.

Some checks are geometric. Did the route violate clearance? Did copper collide with a keepout? Did the layout preserve the design rules required by the fabricator?

Some checks are electrical. Did a controlled-impedance net match the stackup target? Did a differential pair cross a cutout in the reference plane? Did a layer transition preserve return-path continuity? Did the route introduce excessive coupling or a significant impedance discontinuity?

Some decisions should be correct by construction. A differential pair should not have to “learn” that its two traces belong together, or guess at the spacing between them. Where the answer can be calculated from the stackup and impedance target, Quilter uses the solver-backed result directly. The same principle applies throughout the system: use reinforcement learning where search is hard, use computational geometry where geometry can reduce the search space, use classical solvers where physics needs to be calculated, and use exact algorithms where exact methods work better than learned ones.

Quilter applies these checks through Physics Rule Checks, or PRCs, to distinguish them from the DRCs familiar from traditional CAD tools. A DRC asks whether the geometry obeys manufacturing and spacing rules. A PRC asks whether the routed candidate satisfies targeted electrical-behavior constraints: ground-plane coverage under high-speed traces, coupling between differential pairs, return-path continuity across layer changes, and impedance held within tolerance for the stackup. These checks run during candidate generation, not only after routing, so the system can discard bad layouts before it commits to them.

This is what we mean when we say Quilter compiles boards instead of routing nets. The autorouter connected pins. Quilter generates complete layout candidates for supported board classes, with targeted physics checks applied during generation rather than left entirely to post-route review.

That said, PRCs are not a claim of EMI/EMC compliance. Quilter is a component placement and routing system, not a substitute for human review, board bring-up, lab testing, or regulatory compliance work. Quilter does follow layout practices that generally support better electrical behavior, such as preserving unbroken ground reference under microstrip traces to improve signal integrity. These practices can help produce stronger layout candidates, but they do not replace downstream EMC testing or compliance validation.

The Third Missing Piece: Compute at Scale

Cloud computing is the third piece.

Specctra and the autorouters that followed were built to run on a single workstation. Allegro and Altium still ship their routers that way. A local router can only use the computer it runs on, so when a board gets harder, there's no more compute to reach for. You're capped by whatever workstation you have.

That ceiling is most of why autorouters never got past a first attempt or two. The compute to try the next candidate, and the next fifty, wasn't there.

The cloud lifts that limitation, and the scale matters in three ways. First, the model has to be trained, and it learns from millions of practice layouts. Second, the only honest way to know whether a placement works is to route it. Therefore, every promising placement the model tries has to be fully routed just to be considered. Third, the system needs to run many candidate boards through placement, routing and physics checks at the same time, which is far more work than a desktop autorouter could ever handle. 

Quilter runs on AWS cloud infrastructure where the compute resources can be automatically scaled up or down as needed. For teams that can't put their designs in the cloud, ITAR-controlled work or strict IP, Quilter can also be deployed inside your own AWS, Azure or GCP infrastructure, with no design data leaving your network.

What Can AI PCB Layout Tools Do Today?

After decades of false starts, automated PCB layout is worth another look. Not because anyone outsmarted the problem, but because the technological progress in other domains finally made this problem feasible to solve. The pieces above are foundational to Quilter's technology today, but our technology stack will continue to evolve. We're on a mission to solve layout with whatever tools do the job best.

We also have to be transparent about limitations. Quilter is among the more advanced tools on the market attempting to automate layout, but we haven’t solved this problem yet. The sweet spot for us today is boards in the 100 to 1,000 component range, with pin density under 20%, signals up to around 10 GHz, and through-hole vias. Blind and buried vias, BGA fanouts, length matching, and RF are at varying stages of development. You can follow our progress on the changelog. Many teams adopt Quilter by running it end-to-end on the boards it handles well, and on the routine sections of more complex ones while they pre-route the critical parts themselves.

Quilter is evolving fast. The computer we built for Project Speedrun wouldn't have been possible 6 months before we built it. Every board submitted to Quilter exposes a new class of problems to our training pipeline. We don't train on your design; we learn from the problem your design represents. More users means harder problems. Harder problems make Quilter better for everyone using it.

Hardware has watched software go through this evolution. Software engineers once hand-wrote assembly and didn't trust the compiler to do it. Compilers got good enough, and now almost no one writes assembly by hand except in rare, specialized cases.

PCB layout is early on a similar arc. The analogy is not perfect. Boards are physical objects with manufacturing variation, supplier constraints, signal-integrity concerns, and individual artistic tastes. But the direction is similar: the work shifts from hand-drawing every detail toward specifying intent, reviewing candidates, and trusting automation for the parts it can handle well.

The autorouter was a net-completion tool. The next generation has to be a board-compilation system: a tool that takes design intent, constraints, stackup, components, and targeted physics checks, then searches for complete layout candidates that satisfy the actual requirements of the board.

The autorouter was the right idea for its time, and the problem it was trying to solve is still worth solving. We respect that legacy, and are building from it.

Frequently Asked Questions

What is the difference between an autorouter and AI PCB layout? I already have an autorouter in my EDA tool. Why use Quilter?

AI PCB layout is not the same as autorouting.

A traditional autorouter takes placement as a fixed input and connects nets using grid-based, shape-based, or topological routing methods. It usually scores success by completion rate against design rules.

AI PCB layout, in the form Quilter has built, treats placement and routing as one coupled problem. It uses reinforcement learning to navigate the search space, classical solvers to support targeted physics checks, and cloud-scale or customer-controlled compute to explore many candidates in parallel.

The key difference is the objective. The autorouter tries to connect nets. AI PCB layout tries to generate complete layout candidates that are useful, reviewable, and physically valid for supported board classes.

In other words, autorouting is usually net-focused, while AI PCB layout is more system-focused.

Is Quilter just a trained model?

No. Quilter is not just a trained model generating layouts from examples. The system combines reinforcement learning, computational geometry, classical solvers, and exact algorithms. Where a constraint can be handled directly, Quilter tries to do it “right by construction” rather than expecting a model to learn it. For example, differential-pair spacing should be derived from the stackup and impedance target, not guessed by a neural network.

Are PCB autorouters worth using?

Sometimes.

Autorouters can be useful for simple boards, noncritical interconnects, exploratory routing, or as a first pass when the cleanup burden is low. They are less useful when the board is dense, high-speed, highly constrained, or sensitive to placement and routing tradeoffs that change across the design.

The question is not whether an autorouter can connect copper. The question is whether its output saves time or creates more work.

Does Quilter auto-place components or only route?

Quilter does both placement and routing. If components, pre-routes, or copper are already placed inside the PCB boundary, Quilter can preserve them. Components left outside the boundary can be placed automatically, using design context such as bypass-cap assignments, DC-DC converter groupings, crystal oscillators, schematic structure, and placement regions. That is one reason Quilter is different from a traditional autorouter, which usually assumes placement is already fixed.

How much control do I have over the layout?

You have full control and can have Quilter do as much or as little of the layout as you want. You can upload just a board outline with no components placed and have Quilter handle everything from start to finish. Or you can pre-place critical components and pre-route nets, and let Quilter fill the rest. Everything already placed or routed on the board file you upload, Quilter treats as “solved” and will just work around it without making any modifications.

Does Quilter show which constraints were met?

Yes. Quilter provides output that helps engineers understand which identified constraints were met and which still need attention. That matters because AI layout should not be a black box. The designer needs to know where Quilter produced a usable candidate, where human review is required, and where another iteration may be needed.

Does Quilter perform EMI/EMC verification?

No. Quilter does not perform EMI/EMC compliance verification, and we do not claim that any design downloaded after routing is compliant with any particular EMI/EMC rule, standard, or certification requirement.

Quilter is a component placement and routing system. It uses physics, reinforcement learning, solvers, and classical algorithms to generate better layout candidates, but the human engineer remains responsible for reviewing the design, bringing up the board, testing it, and determining whether it meets the applicable compliance requirements.

That said, Quilter does generally follow layout practices that support better signal integrity, such as preserving unbroken ground reference under microstrip traces where appropriate. These practices can improve the quality of layout candidates, but they do not replace downstream EMI/EMC testing or compliance validation.

References

EEVblog Forum. 2014. "Chris Gammell's 'Never Trust the Autorouter' Shirt on Teespring." Discussion thread. https://www.eevblog.com/forum/chat/chris-gammel_s-_never-trust-the-autorouter-shirt_-on-teespring/.

Federal Trade Commission. 1997. "FTC Settlement with Cadence, Cooper & Chyan To Preserve Competition in Automated Chip Design Software." Press release, May 8, 1997. https://www.ftc.gov/news-events/news/press-releases/1997/05/ftc-settlement-cadence-cooper-chyan-preserve-competition-automated-chip-design-software.

Goering, Richard. 2005. "EDA Pioneer Takes Startup to New Routing Ground." EE Times, August 22, 2005. https://www.eetimes.com/eda-pioneer-takes-startup-to-new-routing-ground/.

Hackaday. 2018. "Friday Hack Chat: Trusting the Autorouter." February 21, 2018. https://hackaday.io/event/56777-trusting-the-autorouter/log/100474-trusting-the-autorouter-hack-chat-transcript

Lee, C. Y. 1961. "An Algorithm for Path Connections and Its Applications." IRE Transactions on Electronic Computers EC-10 (3): 346–365. https://doi.org/10.1109/TEC.1961.5219222.

McMurchie, Larry, and Carl Ebeling. 1995. "PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs." In Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays, 111–117. https://doi.org/10.1145/201310.201328.

Silver, David, et al. 2017. "Mastering the Game of Go without Human Knowledge." Nature 550: 354–359. https://doi.org/10.1038/nature24270.

Simonovich, Bert. 2011. "Fiber Weave-Induced Timing Skew." Bert's Practical Design Notes, I-Connect007, September 17, 2011. https://iconnect007.com/article/61693/berts-practical-design-notes-fiber-weaveinduced-timing-skew/61696/design.

TechInsights. 2017. "Apple iPhone X Teardown." Blog post, September 13, 2017, updated November 8, 2017. https://www.techinsights.com/blog/apple-iphone-x-teardown.

Yan, Junchi, Xianglong Lyu, Ruoyu Cheng, and Yibo Lin. 2022. "Towards Machine Learning for Placement and Routing in Chip Design: A Methodological Overview." arXiv preprint arXiv:2202.13564. https://arxiv.org/abs/2202.13564.