Live am 26. März um 9:30 Uhr Pacific

KI-entworfenes Computersystem — Board Bring‑Up

Quilter validiert öffentlich ein KI-entworfenes Computersystem durch Live-Board-Bring‑Up – vom Einschalten bis zur Ausführung realer Workloads.
Keine Folien. Keine Demo. Keine Schnitte.

Reinforcement Learning für das Design von Elektronik-Hardware, die funktioniert.

custom circuit board

Der Board-Bring‑Up ist der Moment, in dem Hardware-Designs der Realität begegnen. Power-Integrität, Signalverhalten, Layoutentscheidungen und Schaltplanannahmen werden vom physischen System getestet – nicht von Simulationen oder Screenshots.

In dieser Session wiederholt Quilter den Bring‑Up- und Validierungsprozess aus Project Speedrun, mit demselben Design und denselben Constraints. Das System wird live eingeschaltet und durch Systeminitialisierung, Betriebssystem-Bring‑Up und anhaltende Workload-Ausführung geführt.

Sollten Probleme auftreten, werden sie in Echtzeit behoben.

Project Speedrun →

Agenda

01

Einen Fertigungspartner finden

  • Replikation des NXP i.MX 8M Mini EVK als Ausgangspunkt
  • Behandlung von Problemen mit Referenzdateien: Formatumwandlung, Dateialter und Lieferkette
  • DFM, DFA und Lagenaufbau-Abstimmung über Hersteller hinweg

02

Baselining mit funktionierenden NXP-Kopien von Sierra

03

Durchgang durch Quilters SOM- und Baseboard-Kandidaten

04

Finale Designs in Altium

05

Live-Board-Bring‑Up

  • NXP-SOM mit unserem Baseboard
  • NXP-Baseboard mit unserem SOM
  • Unser SOM und Baseboard gemeinsam
  • Messungen der Stromversorgung
  • Firmware-Ladung mit NXP-Werkstools
  • Linux-Image-Boot
  • Hardware-Validierung
  • Weston-Desktop- und NXP-GPU-Demos
  • GNOME-Desktop

06

Q&A

Ihr Moderator

Ben Jordan

Staff Electrical Engineer, Quilter

Ben ist Computer Systems Engineer mit einem Bachelor of Engineering (Honors I) der USQ, Australien, und ein IPC CID+ zertifizierter Advanced PCB-Designer. Ben bringt über zwei Jahrzehnte Erfahrung in Electronic Design Automation und Hardware-Engineering auf Systemebene zu Quilter mit, darunter High-Speed-Digital, Audio, HF/µWave, Leistungselektronik sowie Signal-/Power-Integritätsanalyse.

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By Design Type

Test Fixtures & Harnesses

Shave 4–6 weeks off board bring-up

IC Evaluation Boards

Cuts layout cycles from weeks to hours; enables rapid, fabrication-ready design iteration

Design Validation Boards

Shrinks validation cycles from months to days

Backplane & Interconnect Boards

From 30+ days to under 24 hours

By Industry

Semiconductors

Bring-up ready in a single workday (first candidates often appear within the first hour).

Robotics

Compress board bring-up from 4 weeks to under 1 day

Consumer Electronics

Boards ready in a single workday (first candidates often appear within the first hour)

Aerospace & defense

Faster board bring-up for validation and TRR

By Role

R&D managers

Accelerate board bring-up

PCB Designers

Full fab-ready designs in under 4 hours

Electrical engineers

Schematic to fab-ready in under 4 hours

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