Agenda

Recorded April 23, 2026. Sergiy Nesterenko (Founder and CEO) and Richard Whitney (VP of Product) walk through everything Quilter shipped in Q1 2026, demonstrated live in the app rather than on slides: calculated impedance profiles powered by Simbeor, ground net comprehension and region ground pours, a restructured setup flow with computed constraints visible up front, single stackup per job, a full-screen candidate reviewer, and Projects for organised iteration. Plus an early look at clearance constraints read from your files and automated BGA fanouts.

Chapters

  • 00:53 Where Quilter fits — Picking up after your schematic is done: placement, routing, stackup and getting ready for fab.
  • 01:52 Project Speedrun — The i.MX 8M Mini Linux board built to push Quilter hard, and why it drove the year's roadmap.
  • 02:29 What shipped in 2025 — Automated power pours, placement regions and clustering, stackup control, and full keepout support.
  • 04:44 Projects — Jobs grouped by design, unlimited iterations, and billing per project rather than per run.
  • 07:39 Stackup, made explicit — Every layer and its detected purpose shown up front, or swap in a fabricator stackup.
  • 08:07 Fabricator minimums — The absolute design rules Quilter will never go below, so your DRCs pass.
  • 10:13 Circuit comprehension — Differential pairs, power nets and their currents, ground nets, bypass caps and crystals, all as detected.
  • 11:45 Computed constraints — Diff pair widths and gaps solved with Simbeor; power net widths from IPC-2221, by layer.
  • 13:06 Defining your own constraints — Net widths by layer, preserved pours, and confirming placement regions.
  • 14:33 The new candidate reviewer — Placements linked to routed candidates, layer controls, and the design review checks Quilter ran.
  • 18:14 Region ground pours — An isolated ground for a placement region, why it helps, and when not to use it.
  • 20:56 Coming next: clearance constraints — Arbitrary per-net, trace-to-via and board-edge clearances, matched to the rules already in your CAD tool.
  • 22:34 Coming next: BGA fanouts — Escaping each pin to a via and out to the component boundary, also useful for backplane connectors.
  • 25:06 Q&A — On-prem deployment, training on your data, Expedition support, pin swapping, and finding the smallest board that routes.